Current consumer electronic IC devices typically include one or more high-speed memory circuits (e.g., Dynamic Random Access Memory (DRAM) devices) and one or more data processing circuits (e.g., a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), an Application Processor Unit (APU), or a Network Processor Unit (NPU)). The memory and data processing circuits (processors) are typically fabricated on separate semiconductor die (chips) using two different semiconductor fabrication processes in order to minimize overall manufacturing costs, and the separate memory and processor chips communicate with each other by way of signal lines formed on an interconnect structure. In most cases the memory and processor chips are combined in a single multi-chip package, whereby the interconnect structure is implemented using a substrate that is designed and fabricated using techniques similar to those used in the production of printed circuit boards.
Several random-access memory (RAM) interface technologies have been developed to facilitate data transmissions between memory and processor chips. Each of the RAM interface technologies, such as DDR4 or GDDR5, have standardized communication protocols that are implemented by way of interface circuits, typically referred to as physical layers or “PHYs”, which are incorporated into (i.e., fabricated as part of) each memory and processor chip and coupled by way of an intervening interconnect structure. For example, data transferred from the memory chip is first transferred to the memory chip's PHY, then from the memory chip's PHY onto signal lines of an intervening interconnect structure, then from the signal lines through the processor chip's PHY, and finally to the processor circuit. Each PHY receives signals from or transmits signals to an array of contact pads that are disposed in a standardized (predetermined) pattern on the external surface of the multi-chip substrate. The interconnect structure (e.g., a multi-chip substrate) typically includes a corresponding set of interconnect contact pads, which are arranged patterns that mirror the contact pads of the memory and processor PHYs, and signal lines that connect corresponding pairs of interconnect contacts pads, whereby operable connection of memory and processor chips is achieved by way of connecting their respective contact pads to the interconnect contact pads using, for example, solder bumps or other known technique. With this arrangement, an IC device producer is able to reliably combine a selected processor chip with memory chips obtained from different sources, provided the memory chips' PHY is configured using the same RAM interface technology as that of the processor's PHY, which can lead to lower manufacturing costs (i.e., by allowing the IC producer to purchase memory chips from one of several suppliers that is offering the lowest per-chip price) and potential supply-chain-related production delays (i.e., by allowing the IC producer to purchase memory chips from a secondary supplier when a main supplier cannot meet current demand).
The ongoing evolution of consumer electronics requires the continuous development of inexpensive IC devices capable of processing ever-increasing amounts of data at ever-faster processing rates. As advances in semiconductor fabrication processes provide memory and processor chips capable of increasingly faster operating speeds, there is a growing consensus that existing RAM interface technologies may cause the main bottleneck to future improvements in IC device performance.
High Bandwidth Memory (HBM) is a relatively new RAM interface technology that was developed to circumvent the anticipated problems presented by established RAM interface technologies. HBM provides access to larger amounts of memory—currently, up to 16 GB—at faster data throughput—currently 1 to 2 TB/s—than current RAM interface technologies. HBM achieves high capacity by way of a stacked memory chip configuration including two or more memory die mounted on a communication die (referred to herein as an “HBM stack”), and achieves high throughput by way of an ultra-wide communication lane (i.e., 1,728 data signal wires connected in parallel between corresponding PHYs provided on each HBM stack and the host processor).
Although HBM promises at least temporary relief from the impending RAM interface technology bottleneck, implementation of HBM's wide ultra-wide communication lane presents both physical implementation challenges and place-and-route challenges to current IC device manufacturing technologies.
The physical implementation challenge presented by HBM technology is typically addressed by utilizing one or more silicon interposers. That is, a typical HBM-based IC device is a multi-chip-package assembly including a centrally positioned host processor die (e.g., a GPU, a CPU, an APU, or an NPU, collectively referred to below as “xPU”) and two to eight HBM stacks positioned along opposing side edges of the xPU die. With this arrangement, the required interconnect structure must provide, for each HBM stack, a first set of 1,728 interconnect contact pads configured for connection to the HBM stack's PHY, a second set of 1,728 interconnect contact pads configured for connection to an associated PHY on the xPU, and 1,728 signal lines connected between associated contact pads of the two sets. This arrangement is further complicated by optional ground lines that may be disposed between the signal lines. Because currently available packaging technology does not provide package substrates capable of handling such a large number of signal connections, most current HBM device developments involve the use of silicon interposers. Similar to conventional package substrates, silicon interposers are “passive” substrates that do not include active elements (e.g., transistors), only patterned metal signal lines and contact pads that are formed on opposing (i.e., topside and backside) surfaces of a base substrate (i.e., in the case of silicon interposers, a silicon chip), with through-silicon vias (TSVs) that pass through the silicon chip to connecting selected topside signal lines with selected backside signal lines. Unlike package substrates, silicon interposers are fabricated using the same semiconductor processing techniques utilized in IC devices, whereby the line width and spacing of wires formed on a silicon interposer are substantially smaller than those available on current package substrates, thereby facilitating the implementation of HBM's ultra-wide communication lanes. In HBM-based IC devices, the HBM-to-xPU interconnect is typically implemented using only topside metal layers, and the TSVs are utilized for signals transmitted from, e.g., test circuits of the HBM stack and processed data generated by the xPU to an outside system by way of bumps connected to the backside contact pads.
Although silicon interposers are capable of physically implementing HBM's wide ultra-wide communication lane, a second challenge to producing low-cost HBM-based IC devices is the ability to efficiently achieve an interconnect structure routing solution for a given device configuration (placement) using current commercially available automatic routing tools.
The function of an automatic routing tool during place-and-route challenge is illustrated using a greatly simplified example shown in FIGS. 19(A) and 19(B), which depict two ICs 40-1 and 40-2 and an interposer 50, where IC 40-1 includes a three-by-three array of contact pads 41-1, and IC 40-2 includes a corresponding three-by-three array of contact pads 41-2. To generate a functioning IC device, interposer 50 is fabricated according to a layout arrangement generated by a place-and-route tool such that, when ICs 40-1 and 40-2 are mounted on interposer 50 by way of solder balls/bumps 60-1 and 60-2, circuits 49-1 and 49-2 (shown in FIG. 19(B)) are able to communicate by way of contact pads 41-1 and 41-2. The function of the automatic routing tool during the place-and-route process is to generate a pattern of conductive structures (e.g., metal contact pads 51-1 and 51-2 and intervening signal lines 53, shown in FIG. 19(B)) that operably connect each contact pad 41-1 of IC 40-1 with an associated contact pad 41-2 of IC 40-2. The place-and-route process generally begins with a floorplanning phase during which a mounting locations 50-1 and 50-2 (i.e., a “footprint” regions of upper interposer surface 50U occupied by the physical ICs) are selected for ICs 40-1 and 40-2, respectively. Placement typically involves establishing corresponding arrays of contact pads 51-1 and 51-2 inside footprints 50-1 and 50-2, respectively, where contact pads 51-1 and 51-2 are arranged in a mirror pattern to contacts 41-1 and 41-2, respectively, whereby surface mounting during device production is facilitated by way of solder bumps 60-1 and 60-2 (e.g., as illustrated in FIG. 19(B)). Note that the location and pattern of contact pads 51-1 and 51-2 are determined by locations of footprints 50-1 and 50-2, respectively, and by the corresponding fixed pattern of contact pads 41-1 and 41-2. Referring to FIG. 19(B), at this point the automatic routing tool is utilized to generate signal line paths (referred to as “nets” in the industry) that operably connect associated end points (referred to as “pins” in the industry), where the pins to be connected by each net are defined at one end by a contact pad 51-1, and at the other end by an associated contact pad 51-2.
FIGS. 20(A) to 20(D) illustrate in greatly simplified form a typical problem encountered by current commercially available automatic routing tools when providing a routing solution between two sets of pins 52-1 and 52-2 disposed in two-dimensional (2D) planar arrays with both 2D arrays disposed in the same X-Y plane. FIG. 20(A) is a plan view showing the simplified example introduced above, and illustrates an exemplary pattern of nets 53 that must be provided between pins 52-1 and 52-2 by an automatic routing tool, where pins 52-1 and 52-2 in this case are established by the arrays of contact pads 51-1 and 51-2 disposed in footprint regions 50-1 and 50-2, respectively. Note that the pins 52-1 and 52-2 (i.e., routing end points) are indicated by circles in the middle of each contact pad, and the required nets 53 (i.e., signal line connections between associated pins) to be provided by the automatic routing tool are indicated by curved dashed lines. Note that, for purposes of simplification only, this example assumes that the contact pads and all signal lines must be disposed in a single layer (i.e., on upper surface 50U, shown in FIG. 19(A)). FIG. 20(B) shows exemplary early progress by an automatic routing tool in generating initial signal lines 54 between the nets of associated contact pads in the innermost columns of arrays 50-1 and 50-2, and FIG. 20(C) shows subsequent progress by the routing tool to generate secondary signal lines 55 between the nets of associated contact pads disposed in the central columns of arrays 51-1 and 50-2 such that secondary signal lines 55 do not conflict with signal lines 54. FIG. 20(D) shows in simplified form a conflict that can arise when the routing tool attempts to generate additional signal lines 56 between the nets of contact pads in the outer columns of arrays 50-1 and 50-2. Specifically, due to the earlier assignment of routing resources (space) to signal lines 55, the only space available for generating signal lines 56 may produce offset violations OV (indicated by the dashed-line oval regions) between associated portions of signal lines 55 and 56, where a minimum spacing between two metal structures is established by design rules defined by the selected fabrication process, and each offset violation OV is generated when a spacing between the indicated portions of lines 55 and 56 is less than the minimum spacing. The occurrences of such offset violations and other conflicts are addressed by way of reconfiguring the routing solution (i.e., adjusting or repositioning one or more signal lines) to remove the conflict. However, when the automatic routing tool encounters such conflicts during generation of a routing solution between two densely-packed contact pads arrays, such as in HBM-based devices, such adjustments may generate other conflicts, requiring additional adjustments. As mentioned above, for each HBM stack, the required routing solution must provide 1,728 electrically isolated signal lines (i.e., metal wires entirely separated from adjacent wires by an insulating or dielectric material) that are coupled at opposing ends to two sets of contact pads. According to the JEDEC-established HBM contact pad arrangement, the 1,728 contact pads are arranged in 144 rows (i.e., with twelve contact pads in each row), with vertical spacing between rows of a little over 25 microns±10%. Due to the large number of contact pads closely spaced nets, it is easy to understand how automatic routing tools can require significant amounts of time to generate a routing solution, particularly when conflicts arise between the closely spaced signal lines.
Moreover, the routing solution problem mentioned above is further complicated in HBM-based IC devices by the addition of ground lines that extend in parallel with the signal lines. To provide connections to such a large number of densely-packed contact pads, conventional routing solutions call for relatively narrow signal lines (i.e., to maximize wire-to-wire spacing in order to minimize cross-talk). However, depending on relative placement of the HBM and xPU, the contact-pad-to-contact-pad length of the signal lines can be 5 mm, or even longer, which promotes the use of relatively wide signal lines to reduce resistance and associated signal loss. To facilitate relatively wide signal lines while minimizing cross-talk, current HBM-based IC devices sometimes include ground wires or planes that separate the signal lines. Accordingly, the routing solution may have to accommodate as many as 3,600 wires for each HBM-PHY-to-xPU-PHY connection. Moreover, because each HBM-based IC device can include up to eight HBM stacks, an HBM-PHY-to-xPU-PHY routing solution may be required to provide a total of nearly 29,000 HBM-to-xPU wires in a very small space.
Further, in cases where placement produces Y-axis alignment offsets (i.e., mismatches between the HBM stack and host processor preclude the use of single X-axis signal lines), a Manhattan-distance jog or 45° jog (i.e., a wire section extending 45° to standard orthogonal signal lines) may be required. Although digital-type automatic routing tools are capable of handling the large number of nets required in HBM-based IC devices, currently available digital-type automatic routing tools are only capable of implementing Manhattan-distance jogs, which further complicates finding routing problems when Y-axis alignment offsets are present. That is, FIGS. 21(A) to 21(D) show arrays of contact pads 51-1 and 50-2 from the previous example disposed in corresponding footprints 50-1A and 50-2A, where footprint 50-2A has a Y-axis alignment offset (indicated by arrow Y1) from footprint 50-1A. In this case, the routing tool must generate nets 53A that are adjusted from the earlier example to account for the Y-axis alignment offset when providing a routing solution between pins 52 of associated contact pads 51. FIGS. 21(B), 21(C) and 21(D) show the generation of signal lines 54A, 55A and 56A, respectively, each including a Manhattan-distance jog 57 (i.e., two right-angle bends connected by vertical sections having lengths equal to the distance Y1) in order to account for the Y-axis alignment offset between the two arrays. In addition to generating potential spacing conflicts, a problem with utilizing Manhattan-distance jogs is that this approach requires a substantially larger spacing X1 than that required for 45° jogs. Unfortunately, currently available digital-type routers do not accommodate 45° jogs, and currently available analog routers do not have the capacity to deal with several thousands of signals at a time. As a result, custom, heavily manual routing solutions must be devised for each HBM-based IC device, and each manual routing solution must be re-implemented from scratch every time an even minor/small change in the floorplan (i.e., relative placement positions of the HBM stack and processor) is implemented—repeatedly generating such large scale manual routing solutions takes a heavy toll in terms of resources, and can lead to production delays that reduce profitability.
Published U.S. Patent Application US 2014/0117552 A1 discloses an Embedded Multi-Die Interconnect Bridge (EMIB) including a pre-fabricated, fixed pattern of contact pads and shielded signal lines that can be used to interconnect an HBM PHY and a corresponding xPU PHY. That is, because the positioning of the HBM contact pads relative to the xPU contact pads on an EMIB is pre-set (i.e., fixed, cannot be changed), the placement of each HBM stack relative to a host xPU is strictly determined by the EMIB. This inflexibility may become a problem in some applications where a minor shift in the relative placement of one or more HBM stacks might significantly enhance an overall IC device routing solution. That is, there is no way to shift the position of the HBM stack relative to the host processor even a minute amount to utilize package substrate area occupied by the EMIB. Therefore, while the use of EMIBs may provide a suitable interconnect solution in some HBM-based IC device configurations, a device manufacturer cannot use EMIBs when the pre-set HBM-to-processor placement restriction does not meet a desired place-and-route solution, which requires the device manufacturer to implement the time consuming manual routing approach described above.
What is needed is a place-and-route methodology capable of automatically generating routing solutions between two arrays of densely-packed contact pads, such as those found in HBM-based IC devices. In particular, what is needed is a place-and-route methodology capable of automatically generating routing solutions for any placement position of the two densely-packed arrays of contact pads using currently commercially available routing tools, thereby overcoming the deficiencies of the conventional approaches set forth above.